1. Field of the Invention
The present invention relates to a direct-sequence spread spectrum (SS) communication receiver which is used for wireless LAN or a portable telephone, for example, particularly to a receiver which performs synchronization such as symbol synchronization, code synchronization and clock synchronization and synchronization of propagation path characteristics estimation result which is used in a Rake.
2. Description of the Related Art
An existing receiver for spread spectrum communication systems includes an A/D converter which converts a received analog signal to a digital signal; a down converter; a Rake receiver; and a frequency offset correction device connected to the A/D converter, the frequency offset correction device forming a digital feedback loop so as to change the digital signal in accordance with a frequency correction term signal and thereby to correct a frequency offset of the received signal, as disclosed in, for example, Japanese Patent Application Kokai No. H07-115387 (hereinafter, referred to as “JP-A No. H07-115387”).
Furthermore, in the timing error detection in a configuration where the direct-sequence spread spectrum (SS) communication is not used, an early gate algorithm is applied, or an interpolation circuit is applied in a symbol synchronization circuit, as disclosed in “Interpolation in Digital Modems Part I”, F. M. Gardner, IEEE TRANSACTIONS ON COMMUNICATIONS, VOL. 41, No.3, MARCH 1993 (hereinafter, referred to as “non-patent literatures 1”); and “Interpolation in Digital Modems Part II”, L. Erup, F. M. Gardner and R. A. Harris, IEEE TRANSACTIONS ON COMMUNICATIONS, Vol.41, No.3, MARCH 1993(hereinafter, referred to as “non-patent literatures 2”).
Reference can also be had to Japanese Patent Applications Kokai No.H09-107310 and No.H07-312571, and “A BPSK/QPSK Timing-Error Detector for Sampled Receivers”, F. M. Gardner, IEEE TRANSACTIONS ON COMMUNICATIONS, VOL.COM-34, No.5, pp.423-429, MAY 1986(hereinafter, referred to as “non-patent literatures 3”).
However, in the JP-A No.H07-115387 reference, since a down conversion circuit is applied in a clock synchronization circuit necessary for the signal synchronization, an interface between an RF section and a baseband section is closely coupled, when a constitution of a receiver is roughly divided into the radio-frequency (RF) section and the baseband section. Accordingly, for instance, there is a problem in that, when an LSI for the RF section and an LSI for the baseband section are purchased, it is necessitated to purchase LSI's in combination of products of the same company.
Furthermore, a synchronization circuit such as shown in the non-patent literatures 1 and 2 has a configuration which does not use the direct-sequence spread spectrum communication scheme; accordingly, simply, it could not be applied to the SS communications. For instance, the circuit does not have a configuration which technically satisfies processing of the symbol synchronization, code synchronization and clock synchronization in the same function.